Multiphase Clock (DSP Blockset)

Generate multiple binary clock signals.

Library

Switches and Counters, in General DSP

Description

The Multiphase Clock block generates a vector of N clock signals, where N is specified by the Number of phases parameter. All phases share the same frequency, f, specified in Hertz by the Clock frequency parameter.

The output signal indexed by the Starting phase parameter is the first to become active, at t=0. The other signals in the output vector become active in turn, each one following the preceding signal's activation by 1/(N*f) seconds, the phase interval. The output sample period is therefore 1/(N*f) seconds.

For example, if Starting phase is set to 3 for a 100 Hz five-phase output y, the output signals become active at the following times.


Signal	Output	Becomes Active at Time:
3	`y(3)`	t = 0.000, 0.010, 0.020, 0.030, ...
4	`y(4)`	t = 0.002, 0.012, 0.022, 0.032, ...
5	`y(5)`	t = 0.004, 0.014, 0.024, 0.034, ...
1	`y(1)`	t = 0.006, 0.016, 0.026, 0.036, ...
2	`y(2)`	t = 0.008, 0.018, 0.028, 0.038, ...

The first Scope window below shows the Multiphase Clock block's output for these settings. Note that the first active level appears at t=0 on y(3), the second active level appears at t=0.002 on y(4), the third active level appears at t=0.004 on y(5), the fourth active level appears at t=0.006 on y(1), and the fifth active level appears at t=0.008 on y(2). Each signal becomes active 1/(5*100) seconds after the previous signal.

The active level can be either high (1) or low (0), as specified by the Active level (polarity) parameter. The duration of the active level, D, is set by the Number of phase intervals over which the clock is active. This value, which can be an integer value between 1 and N-1, specifies the number of phase intervals that each signal should remain in the active state after becoming active. The active duty cycle of the signal is D/N. (The Scope window immediately below illustrates an Active level setting of High and a Number of phase intervals over which clock is active setting of 1.)

The Scope below shows Signals 1 and 2 with an active-level (high) duration of three phase intervals (60% duty cycle), corresponding to a setting of 3 for Number of phase intervals over which clock is active.

Dialog Box

Clock frequency: The frequency of all output clock signals.
Number of phases: The number of different phases in the output vector.
Starting phase: The vector index of the output signal to first become active.
Number of phase intervals over which clock is active: The duration of the active level for every output signal.
Active level: The active level, high (1) or low (0).